The present invention is related generally to semiconductor fabrication and, more particularly, to a method for removal of photoresist and residues following high dose ion implantation.
The photoresist (PR) stripping applications that will soon be used in the early stages of IC fabrication, just following ion implantation are specialized and difficult. Leading edge logic devices at the 65 nm technology node and beyond may have 15 or more high dose implanted (HDI) photoresist removal steps. The most critical of these stripping processes are those performed after high dose ion implantation into the junctions—which will be extremely shallow (ultra shallow junctions—or USJ). In many cases, six or more of the high dose implantation steps will be performed to form junctions for transistors in fast logic ICs. During the ensuing stripping/cleaning processes of the implanted photoresist, these areas of the silicon surface are often exposed to aggressive plasma chemistries. Also critical will be a few other implanted photoresist removal and cleaning processes that will be performed with gate electrodes exposed—especially at about the 45 nm technology node and below, when gates will be made of metals or metal silicide. Of course, all junctions are exposed during wet chemical cleaning processes that virtually always follow the dry stripping processes.
Recently, we have found that the combination of even the most non-damaging dry stripping processes with even the softest wet cleaning processes which are needed to fully remove crust, photoresist and residues, cause loss or oxidation of silicon at transistor junctions beyond the acceptable limit for 45 nm devices (as listed in the International Technology Roadmap for Semiconductors—ITRS). It is submitted that current PR stripping, residue removal or surface treatment processes for these applications will be inadequate to meet all process requirements for future device nodes, as the size of transistors continues to shrink and the thickness of critical silicon layers on the wafer surface continues to decrease.
One important reason is recognized to be the difficulty in complete removal of the PR where the top layer of the PR has been subjected to very substantial ion bombardment (during ion implant doping) that causes most hydrogen in the polymer to be lost and the carbon in the polymer to cross-link. The toughness of the top layer of the implanted PR (implant crust) is well known, and makes it highly resistant to the chemical attack that is commonly used to strip the photoresist. The physical structure of the resist after high dose ion implantation is shown in FIG. 1, generally indicated by the reference number 100. A first layer 101 is a hardened “crust” which received most of the ion dose when it was used as a mask during implantation. Research has shown that the crust is a graphitic, highly cross-linked, and predominantly a carbon polymer when the dose of ions is equal to or greater than 1015 per centimeter squared. Typically, the implanted ion energy is such that the ions do not penetrate more than a fraction of the thickness of the photoresist mask. Consequently, the ion-damaged crust is only a fraction of the thickness of the photoresist. The remaining PR (so called “bulk”), which has not been ion implanted, is indicated by the reference number 102, It can be seen that the crust and the bulk PR contact silicon 103, with the crust partially or completely enveloping the bulk.
Because of the hardness and low reactivity of the PR crust material, the dopants in the crust and the tendency of normal stripping processes to cause particulate contamination on the wafer, processes for removing high dose implanted PR are very difficult. Historically, because of the toughness of the implanted crust, and the fact that the crust contains dopant atoms and some silicon on its sidewalls, the first one or two removal steps are performed with plasma-based dry stripping systems, while the final cleaning step for removing residues remaining after stripping is often performed with strong aqueous chemicals—usually in chemical baths. During such processes it has been normal for a modest amount of the silicon dioxide surface material covering the junctions of transistors to be lost. However, recent advances in integrated circuit technology require preservation of the ion implanted dopants at the top layers of the junctions, and as a result it is thought that the sacrificial oxide layer that has been used in most device generations to protect junctions can not be used in future technology nodes.
A schematic of a standard configuration of a downstream plasma-based PR stripping chamber and source is shown in FIG. 2, generally indicated by the reference number 200. Gas coming from a set of flow controllers and valves 201, passes via tubing 202 to a plasma source 203. There, the gas becomes substantially dissociated (and partially ionized) and then goes through a distribution/baffling system 204 into a wafer process enclosure 205. A pedestal 206 holds a wafer 207 that is to be stripped of PR and residues. On the wafer, radicals react with the PR and residues to form volatile or water-soluble reaction products that are then pumped out by ducts 208 or later rinsed off the wafer. This type of PR stripping chamber is widely used because it provides almost entirely neutral reactive species to strip the PR and does not subject the wafer to large amounts of charged particles, especially energetic ones that might damage the sensitive materials and layers used in making the integrated circuits. Such stripping systems are generally used for removing PR during the early stages of IC fabrication, when the transistors are fabricated. Removal of photoresist following high dose ion implantation is much slower and more difficult due to the implanted and slowly-reacting carbon-based crust layer that covers and protects the volume of bulk photoresist that did not receive much or any ion implantation damage. It should be appreciated that system 200 is readily adaptable for purposes of implementing a wide range of processing conditions, including those yet to be described.
In order to strip the photoresist with high productivity in a plasma-based downstream dry stripping process it is usually desirable to make the wafer temperature as high as possible (˜200 C. to 250 C.) so as to increase reaction rates and consequently the stripping rate (to achieve high throughput and productivity). However, for implanted photoresist, the implanted crust has only very slow chemical reactions with reactive radicals, as compared with non-implanted photoresist. When wafers are stripped following high dose implant (HDI) in a high-temperature (>150 Celsius) conventional dry stripping process, rupture (“popping”) of the photoresist crust may occur, causing higher than desirable particulate and defect levels on the wafer. In this “popping”, the high temperature is believed to cause solvents contained in the bulk resist to go into the gas phase and pressure to build up underneath the crust. When the pressure builds sufficiently, it causes the hardened crust to rupture or detach from the bulk PR as it vents the built-up pressure. In conventional high temperature stripping of such HDI PR, popping is tolerated. Once the crust pops, the exposed bulk PR quickly etches in standard oxygen-based stripping processes—normally performed with wafer temperatures between 200 Celsius and 300 Celsius. Most fragments of crust are consumed in the dry stripping process but most of those that remain are physically and chemically removed by a wet bath clean. However, some such fragments are hard to remove by normal wet cleaning and cause excessive defect levels and resulting loss of IC yield. However, if the process temperature is reduced below about 120 C. to 140 C. to avoid popping, then the low reactivity of the crust can cause the process to take an extremely long time—up to tens of minutes—which is very expensive due to its reduction of stripping system productivity. This is unacceptable for the economics of IC devices, which must increasingly go into affordable consumer products.
Since the hardened crust, unlike bulk PR, is very hard to strip even with the most reactive radicals such as atomic oxygen, and especially so at low enough temperatures to eliminate popping, other means of activation of chemical reactions have been found to activate reactions—such as described in U.S. Pat. No. 4,861,424 to Fujimura (hereinafter the '424 patent) and U.S. Pat. No. 6,805,139 to Savas et al. Generally, ion bombardment in an etching type of system is used to etch the top crust of the photoresist at low temperature (<120 C.) and then a higher temperature downstream, thermal activation type of stripping step, and/or conventional wet cleaning method is used to remove the remaining photoresist, sidewall crust and residues. A frequent second step to remove much or all of the remaining bulk PR (which has not been chemically altered during the ion implantation) may be performed at higher wafer temperature (normally at least 200 Celsius) than the crust etching step—to speed up the etching rate. Thus, after the crust is breached, there is no further danger of popping, since pressure cannot build up, and the temperature may be higher. At this stage, the bulk PR is accessible to the gas phase species and such photoresist, not altered by ion implantation, quickly etches chemically. This step is very similar to normal PR stripping applications, since the under layer of photoresist has been substantially unchanged by the patterning or doping process.
However, the stripping of the bulk photoresist is not normally the final step, due to the significant side effects of ion implantation. Very often, difficult to remove residues remain after removing most of the crust and all the bulk PR. Such residues are usually made up of the remnants of the implanted resist crust (carbon polymer, dopants and silicon oxide). Usually, silicon compounds are found mostly on the sidewalls of the photoresist, whereas most dopants are found inside the crust. The ion implantation process always causes some silicon dioxide or silicon exposed on the wafer surface to be sputtered. Such sputtered silicon will, in part, strike and condense on the sidewalls or top of the photoresist structures, leaving one or more monolayers of silicon or silicon dioxide on the outer surface of the sidewall crust. This material does not normally (especially in oxygen-based stripping) chemically convert to loose and soluble form during the bulk resist step and may be chemically quite resistant. Therefore, a necessary final step in removal of implanted PR is often the residue removal step. This may or may not be performed in the same system as the first two steps because it may in part require use of wet chemicals including strong acids or bases. When it is performed in part in the same system used for crust and bulk stripping, it usually involves the use of gas additives to the normal oxygen gas injected into the plasma source. Common additives are fluorinated gases as well as mixtures containing nitrogen and/or hydrogen, particularly “forming gas” (FG) which is at least 90% nitrogen or noble inert gas and the remainder hydrogen. Such additives help to convert the residues to a water-soluble form that will be removed by a deionized (DI) water rinse. It is common for such residue removal steps to still leave some un-reacted residues that are not even removed in a subsequent DI water rinse. Such remnant residues will need to be removed by a wet chemical treatment since the wafers need to be completely clean prior to the following process, high temperature thermal annealing of the dopant in the silicon.
High dose implanted PR crust etching using hydrogen-containing gas mixtures (mainly forming gas which is often a mixture of 3% to 5% hydrogen in nitrogen), rather than oxygen was first performed prior to the sub-micron semiconductor technology era in a few factories (Fujimura—previously cited). Conventional reactive ion etching systems (RIE) using Forming Gas were found to be capable of removing the hardened crust on the PR surface formed by high dose ion implantation, at low wafer temperatures to avoid “popping”. The ion-based stripping treatment reduced the number of particulate defects found on the wafer surface following stripping of the implanted PR. In particular, when the RIE systems used this gas mixture they successfully removed the crust (without throwing off particulates by “popping”) so that a following softer step, usually employing a flow of oxygen radicals could then remove the remaining bulk PR. This process worked for IC fabrication technology of that era because the bombardment of the wafer by energetic ions from the plasma provided energy to activate chemical reactions of radicals with the carbon polymer of the crust. This was performed at low temperature to avoid popping which avoided the pervasive problem of particle contamination on the wafer. It is believed that such processes cause sputter loss of several to ten angstroms of silicon dioxide from the screen (sacrificial) layer, as well as implantation of hydrogen and nitrogen between fifty and one hundred Angstroms into the wafer surface. At that time, thickness of silicon dioxide screen layers above the silicon of the junctions were on the order of 100 Angstroms thick, protecting the sensitive silicon from damage or loss due to sputtering or implantation of hydrogen or nitrogen atoms from the stripping process. As no such protection is possible with current and future generations of ICs, there remains a need for photoresist stripping processes that do not significantly remove, damage or oxidize the silicon in the very thin junction areas. It has been found that known stripping processes for implanted photoresist, whether employing downstream neutral radicals for processing wafers at elevated temperatures or utilizing ion-bombardment in a first step at lower temperature by themselves or when combined with wet cleaning processes for removing residues, result in unacceptable silicon loss from the ultra shallow transistor junctions.
More recently, using soft ion bombardment of wafers at lower temperatures, mainly with oxygen ions, has been proposed as a method for removing the crust of implanted photoresist. This method is employed as a first step in the total removal of the photoresist. It is typically followed by a downstream oxygen-radical-based conventional stripping process at higher temperatures, which removes the remaining photoresist. Water rinsing of the wafer or other soft wet cleaning may then be employed to remove the residual inorganic ash remaining after such combined treatment. Applicants have found, as will be further described below, that even the lowest energy ion treatment with molecular oxygen ions causes ion damage and some oxygen ion implantation into the silicon to a depth such that 3 or more monolayers (˜>9 Angstroms) of silicon are damaged by such ion action. Applicants have further found that the ensuing wet cleaning, even with dilute chemicals at low temperatures, causes increased etching of the silicon dioxide from the surface due to the ion damage that may have been caused by the dry etching process. This results in increased oxidation of silicon under the pre-existing silicon dioxide layer by any later wet cleaning process. Consequently, we find that any such stripping process when combined with wet cleaning processes, whether for that layer of photoresist or a later-applied layer, will cause oxidation of (and eventual loss) of more than the acceptable limit, roughly 8 Angstroms to 10 Angstroms (approximately 8-10 Angstroms of total silicon loss is acceptable at approximately the 32 nm device node), of silicon at the surface of the ultra shallow junctions for transistors on the wafer surface.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.
The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods which are meant to be exemplary and illustrative, not limiting in scope. In various embodiments, one or more of the above-described problems have been reduced or eliminated, while other embodiments are directed to other improvements.